The disclosed invention relates to the field of integrated circuit semiconductor manufacture. More specifically, a procedure is disclosed for prevention of the phenomena of dishing of copper which occurs during chemical-mechanical polishing (CMP) of copper.
Metal films are used for a variety of purposes in the fabrication of integrated circuits. For example, it is well-known that metal films may be used to form interconnective lines, contacts and other conductive features on and above the surface of a semiconductor wafer.
In recent years, there has been a growing interest in the use of copper and copper alloys for metallization in integrated circuits. Copper has some characteristics that make it a particularly attractive candidate for metal features. In particular, copper has a lower resistivity than aluminum alloys, and copper is not as susceptible to electromigration as aluminum alloys are.
Semiconductor fabrication generally comprises providing tungsten or copper wiring or metallization in discrete layers of dielectric oxide film. Oxides typically used to form these film layers include phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or silicon dioxide (SiO2). The oxide layer is then planarized using conventional planarization techniques. Thereafter, the oxide layer is etched or otherwise processed to pattern a series of trenches and holes therein. A thin barrier layer is then deposited over the oxide layer. The barrier layer generally comprises thin films of titanium (Ti) and titanium nitride (TiN) disposed over one another to form a Ti/TiN stack, or tantalum (Ta) and tantalum nitride (TaN) to form a Ta/TaN stack. Such a barrier layer is commonly deposited by physical vapor deposition (PVD), otherwise known as sputter deposition, or it may be deposited by a chemical vapor deposition (CVD) to form a more conformed coating. Accordingly, the barrier layer serves to coat the surfaces of the trenches and holes as well as the upper surface of the oxide layer and is used to provide good adhesion between the metallization layer and the oxide layer. The metallization is then provided by depositing a layer of conductive material, such as tungsten (W) or copper (Cu), over the barrier layer, wherein the W or Cu will completely fill the trenches and holes. The filled trenches thus form lines, damascene, or a xe2x80x9cglobal wiring layerxe2x80x9d while the filled holes comprise studs or vias, also known as xe2x80x9clocal interconnectsxe2x80x9d. Fabrication of the wiring layer is then completed by removing the barrier layer and the tungsten or copper layer from the surface of the oxide film. This is typically accomplished by the use of a planarization technique.
There are numerous known methods of planarizing wafers during fabrication of integrated circuits, for example, block resist and resist etch back, block resist and spin on glass, etc. A method of choice is chemical mechanical polishing (CMP). CMP provides full wafer planarization. However, one of the difficulties encountered with CMP for trench planarization is the xe2x80x9cdishingxe2x80x9d effect which occurs in trenches typically of a fully recessed field structure and is related to mechanical polishing of Cu (elastic and plastic). xe2x80x9cDishingxe2x80x9d is particularly severe in wide trenches and the xe2x80x9cdishingxe2x80x9d effect during polishing results in thinning of the dielectric material in wide trenches resulting in dielectric erosion.
One method of forming semiconductors/integrated circuits involves a process known as a damascene process. A damascene process produces conductive interconnects and other features which are directly defined by chemical mechanical polishing. A conventional damascene process begins by forming a dielectric, such as oxide, over a wafer substrate. The dielectric is patterned, for example using lithography to form a photo-resist layer. Troughs are formed in the dielectric defined on two sides by the dielectric and on the bottom by the substrate or a barrier layer. Typically, the barrier layer is also formed on the two side walls of the trough. A conformal blanket layer of conductive material such as copper or tungsten is deposited over the wafer surface. Finally, the wafer surface is polished thereby removing the conductive material overburden while leaving the conductive material in the planar dielectric surface.
In a typical single or dual damascene structure, dishing of copper is a consequence of different polish rates during CMP due to pattern density variations across the substrate. This causes certain areas on the chip where copper is completely removed exposing the underneath barrier layer (typically Ta or TaN) to the polishing slurry, whereas certain other areas still have copper remaining over the substrates surface. In the attempt to completely polish off both the copper and barrier layer, the exposed copper over the trench areas gets over-polished. This over-polish causes dishing of copper.
A related problem of xe2x80x9cerosionxe2x80x9d occurs when there is an excessive loss of the dielectric film (underneath the barrier) due to over-polish during CMP in an attempt to completely remove the barrier layer. Both dishing and erosion are severe problems facing CMP today. Much, effort has been directed to modify the polish process, equipment and materials in attempting to reduce and control the dishing effect.
The above process is more clearly depicted in FIGS. 2A-2C. Trenched regions 22 are defined in the substrate by a conventional method such as photoengraving, anisotropic etching, or other conventional etching and engraving techniques. A barrier layer 24 of a refractory metal (or a refractory metal complex) such as titanium, titanium nitride, tungsten, tungsten nitride or a complex thereof, is usually formed on the surface of the substrate to provide an adhesive layer for the conductive copper material, shown as layer 26, which is deposited thereon. Optionally, a seed layer (not shown) of the conductive material (such as copper) is deposited on the barrier layer to enhance the adhesion of the conductive material.
In order to make a finalized product, the excess copper extending above the trench or vias, along with the barrier layer deposited on the top surface of the substrate, requires removal leaving a planar surface on the wafer substrate while the trench remains filled with the conductive material. A planarization technique, such as a chemical mechanical polishing (CMP) process is utilized to remove of the excess copper and barrier layer.
Chemical Mechanical Polishing is a semiconductor planarization technique that uses a chemical slurry, along with a polishing pad, to xe2x80x9cplanarizexe2x80x9d or remove discontinuities along the surface of an in-process semiconductor wafer. In chemical mechanical polishing, mechanical movement of a polishing pad relative to the wafer in the presence of an abrasive provides mechanical stress which is combined with a chemical process to selectively remove exposed portions of the surface of the wafer. The slurry serves multiple roles; namely, it is the medium in which the abrasive particles is dispersed, and secondly it furnishes the chemical agents which promote the chemical process. In order for optimum results in chemical mechanical polishing, a synergistic relationship between the chemical and mechanical processes typically exists.
In the prior art, a chemical mechanical polishing process is used to effectuate removal of the upper portion of the copper layer 26, as shown in FIG. 2B, leaving the barrier layer 24 and a portion of the copper layer 26 above the top surface of the substrate 20. In attempting to form a planar surface of the substrate 20, the barrier layer 24 and a portion of the copper remaining above the top edge of the trench 22 is polished by CMP. It is during this polishing phase that dishing (shown at 27) of the copper remaining in the trench occurs as shown in FIG. 2C, resulting in a non-planar surface. This is due to the difference in hardness between the barrier layer, which is relatively hard compared to the copper, causing the barrier layer to polish at a slower rate than the copper. As the CMP polishing pad pushes down on the surface being polished, the copper is polished quicker relative to the barrier layer, thereby forming an uneven surface as the barrier layer is removed.
In order to address the prior art problem of dishing as described above, a process according to the present invention, as shown in FIGS. 3A-3F is utilized thereby reducing, or even eliminating, the dishing phenomenon.
The present invention is directed to addressing the problem of dishing of copper during chemical-mechanical polishing (CMP) to provide a planarized surface in the manufacture of integrated circuits/semi-conductors.
According to the present invention, the dishing of copper during chemical mechanical polishing (CMP) can be significantly reduced, and in some instances eliminated, by the local area deposition of a copper alloy. The copper alloy may be formed from copper and a metal which forms a continuous solid solution with the copper. By forming alloys of copper with metals that form continuous solid solutions therewith, a local area deposition layer of such an alloy on the surface of a barrier metal layer over a recessed area filled with a conductive material allows for lowering the selectivity of the slurry polish used during the CMP process towards the conductive material. The alloys of copper with metals that form a continuous solid solution therewith is thought to change the oxidation characteristics, mechanical properties, electrical properties, stiffness parameters and hardness parameters of the copper. The change in these properties may allow the alloy layer to be polished at a more equivalent rate to the barrier layer than a non-alloy copper layer. In this manner, dishing of the copper in the recessed areas (trenches) of a semiconductor or integrated circuit (or similar device) from the CMP process can be avoided as the polish rates between the barrier layer and the copper alloy approach a 1:1 ratio.
Additional advantages and objects of the invention will be realized upon a reading of the following detailed description taken in conjunction with the drawings contained herein.